1. Field of the Invention
The present invention relates generally to methods for forming aperture fill layers within apertures within substrates employed within microelectronic fabrications. More particularly, the present invention relates to methods for forming planarized aperture fill layers within apertures within substrates employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become common in the art of microelectronic fabrication, and in particular within the art of semiconductor integrated circuit microelectronic fabrication, to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronic fabrications trench isolation regions which are nominally co-planar with adjoining active regions of the semiconductor substrate within which are formed the trench isolation regions. Trench isolation regions which are nominally co-planar with adjoining active regions of a semiconductor substrate are desirable within the art of semiconductor integrated circuit microelectronic fabrication, since such trench isolation regions when nominally co-planar with adjoining active regions of a semiconductor substrate most favorably accommodate an attenuated depth of focus of a photoexposure apparatus typically employed in defining patterned microelectronic layers upon the semiconductor substrate having the nominally co-planar trench isolation regions and active regions formed therein.
While trench isolation methods are thus desirable in the art of microelectronic fabrication, and particularly in the art of semiconductor integrated circuit microelectronic fabrication, for forming trench isolation regions nominally co-planar with adjoining active regions of a semiconductor substrate separated by the trench isolation regions, trench isolation regions formed employing trench isolation methods are nonetheless not formed entirely without problems within the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication. In particular, it is observed when forming trench isolation regions nominally co-planar with adjoining active regions of a semiconductor substrate that the trench isolation regions are often difficult to form with enhanced linewidth control and enhanced surface planarity, particularly when forming the trench isolation regions while employing a chemical mechanical polish (CMP) planarizing method.
It is thus towards the goal of forming within silicon semiconductor substrates employed within semiconductor integrated circuit microelectronic fabrications trench isolation regions with enhanced linewidth control and enhanced planarity that the present invention is most specifically directed. In a more general sense, the present invention is also directed towards the goal of forming within microelectronic fabrications which need not necessarily be semiconductor integrated circuit microelectronic fabrications planarized aperture fill layers within apertures within microelectronic layers, where the planarized aperture fill layers are formed with enhanced linewidth control and with enhanced planarity.
Various methods have been disclosed in the art of microelectronic fabrication for fabricating silicon containing layers within microelectronic fabrications.
For example, Babie et al., in U.S. Pat. No. 5,431,772, discloses a plasma etch method for forming from a silicon nitride layer in turn formed upon a silicon oxide layer within a microelectronic fabrication, where the silicon nitride layer has formed upon its surface opposite the silicon oxide layer a silicon oxide containing surface layer, a patterned silicon nitride layer with a plasma etch selectivity of the patterned silicon nitride layer with respect to the silicon oxide layer. The plasma etch method employs: (1) a first plasma employing a first etchant gas composition comprising a fluorine containing etchant gas and an optional hydrogen bromide etchant gas, in absence of an oxidant etchant gas, for etching through the silicon oxide containing surface layer formed upon the silicon nitride layer, followed by; (2) a second plasma employing a second etchant gas composition comprising a hydrogen bromide etchant gas, an optional fluorine containing etchant gas and an oxidant etchant gas, for etching a bulk of the silicon nitride layer to form the patterned silicon nitride layer with the plasma etch selectivity of the patterned silicon nitride layer with respect to the silicon oxide layer.
In addition, Keller, in U.S. Pat. No. 5,644,153, also discloses a plasma etch method for forming from a silicon nitride layer formed upon a silicon oxide layer within a microelectronic fabrication a patterned silicon nitride layer, where the patterned silicon nitride layer is formed with uniform critical dimension control and with a plasma etch selectivity of the patterned silicon nitride layer with respect to the silicon oxide layer. To realize the foregoing objects, the plasma etch method comprises a two step plasma etch method which employs: (1) a first plasma employing a first etchant gas composition comprising a fluorocarbon etchant gas to form from the silicon nitride layer a partially etched silicon nitride layer having a sidewall polymer residue formed thereupon, followed by; (2) a second plasma employing a second etchant gas composition comprising a hydrogen bromide etchant gas and a nitrogen trifluoride etchant gas employed under conditions of high plasma pressure and low plasma power to form from the partially etched silicon nitride layer the patterned silicon nitride layer with the uniform linewidth control of the patterned silicon nitride layer and the plasma etch selectivity of the patterned silicon nitride layer with respect to the silicon oxide layer.
Further, Jang et al., in U.S. Pat. No. 5,726,090, discloses a method for forming, with enhanced gap filling properties and enhanced step coverage properties, within an isolation trench employed within a silicon semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication, a silicon oxide trench isolation region formed employing an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method. The method employs forming within the isolation trench: (1) a first silicon oxide trench liner layer formed employing a thermal oxidation method, the first silicon oxide trench liner layer having formed thereupon; (2) a second silicon oxide trench liner layer formed employing a plasma enhanced chemical vapor deposition method employing silane as a silicon source material, where the second silicon oxide trench liner layer is nitrogen plasma treated prior to forming thereupon the silicon oxide trench isolation region formed employing the ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
Finally, Brooks et al., in U.S. Pat. No. 5,786,276, discloses yet another plasma etch method for forming within a microelectronic fabrication from a silicon nitride layer formed upon a silicon oxide layer a patterned silicon nitride layer with a plasma etch selectivity of the patterned silicon nitride layer with respect to the silicon oxide layer. The plasma etch method employs a downstream plasma employing a single etchant gas composition comprising: (1) a fluoromethane etchant gas or a difluoromethane etchant gas; (2) a carbon tetrafluoride etchant gas and; (3) an oxygen etchant gas, at a composite molar ratio of the fluoromethane etchant gas or the difluoromethane etchant gas, with respect to the carbon tetrafluoride etchant gas, further with respect to oxygen etchant gas, the composite molar ratio selected such that the desired plasma etch selectivity of the patterned silicon nitride layer with respect to the silicon oxide layer is realized.
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed for forming within isolation trenches within silicon semiconductor substrates employed within semiconductor integrated circuit microelectronic fabrications trench isolation regions with enhanced linewidth control and enhanced planarity. More generally desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within apertures within microelectronic layers employed within microelectronic fabrications planarized aperture fill layers with enhanced linewidth control and enhanced planarity.
It is towards the foregoing objects that the present invention is both specifically and more generally directed.